That value will get latched to the outputs for the time between the two latch pulses. That's not a problem since the shift register still has the previous value from the last transfer.īut if there are other devices on the SPI bus, when the latch is pulsed that first time, the '595 shift register will have whatever was the last byte sent to the other device. This will once again latch the '595 shift register to its outputs. Then, when you do the next transfer, the first thing that happens is the CS line is pulsed. If there are other devices using the same SPI bus (with a different CS) this will fall apart. I questioned this at first, but as I think about it, it looks like it will work, but only if these shift registers are the only thing on the bus. You can't do this with shiftin() and shiftout() since they are unidirectional, but you can do it with SPI.transfer() or by manually bit-banging the interface.ĬrossRoads: digitalWrite (latchPin, LOW) ĭigitalWrite (latchPin, HIGH) // captures data on '165 inputsĭataIn = SPI.transfer(dataOut) // read in from '165 while writing out to '595ĭigitalWrite (latchPin, HIGH) // move data to output of '595 When done, the internal shift register holds the input byte. As the bits are shifted out MOSI from one end, it is shifting in bits from MISO on the other end. You start by loading the register with the output byte, then the hardware starts clocking the shift register. The SPI hardware in the processor has a shift register. Sounds like he's trying to make a normal SPI bus, which always operates bidirectionally, although often we ignore the input or output side of a particular transfer.
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